By Leena Singh
"As chip dimension and complexity keeps to develop exponentially, the demanding situations of sensible verification have gotten a serious factor within the electronics undefined. it truly is now usually heard that logical blunders ignored in the course of sensible verification are the most typical reason for chip re-spins, and that the prices linked to practical verification at the moment are outweighing the prices of chip layout. to deal with those demanding situations engineers are more and more hoping on new layout and verification methodologies and languages. Transaction-based layout and verification, limited random stimulus new release, sensible insurance research, and assertion-based verification are all innovations that complicated layout and verification groups regularly use this present day. Engineers also are more and more turning to layout and verification versions in accordance with C/C++ and SystemC which will construct extra summary, better functionality and software program versions and to flee the constraints of RTL HDLs. This new publication, complex Verification Techniques, provides particular counsel for those complicated verification options. The e-book contains lifelike examples and indicates how SystemC and SCV could be utilized to quite a few complicated layout and verification tasks."
- Stuart Swan
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Additional info for Advanced verification techniques : a systemC based approach for successful tapeout
VN-Cover: Works with BHDL, Verilog or mixed language designs. Supports automatic FSM extraction, analysis and FSM path coverage. Provides coverage metrics for statement, branch, condition, path, triggering, trace, toggle, circuit activity analysis, FSM, State Arc, and Path coverage. Covermeter: Verilog code coverage tool that provides comprehensive coverage with features such as testbench grading, automatic extraction of FSMs, toggle coverage, source-line coverage, condition coverage, expression coverage, good performance and GUI.
Lines 2,3 are detailed description pointing to the actual tbvReceiveTaskT. 30 Advanced Verification Techniques Line 4 uses “\param” to describe parameter “key” of the process function. This way all the parameters can be defined. Remembering this information while writing the code‚ can automatically generate quite good documents using Doxygen. html As an example‚ one of the outputs from Doxygen is for dataCom class defined in testBuilder(initial version of SCV)as shown in figure 2-2‚ Inheritance diagram for class tbvDataComT: Figure 2-2.
For more details please refer to Regression chapter. 12 Functional Coverage Functional Coverage is the determination of how much functionality of a design has been exercised by a verification environment. It requires the development of a list of functionality to be checked, the collection of data that shows the functionality of concern being exercised, and the analysis of the collected data. Functional coverage doesn’t prove that the design properly executed the function, just that it was exercised.
Advanced verification techniques : a systemC based approach for successful tapeout by Leena Singh